1. Field of the Invention
The invention relates to a method and apparatus for depositing a tantalum-containing layer on a substrate. More particularly, the invention relates to a method and apparatus for sputter depositing tantalum and/or tantalum nitride layers using a self-ionized plasma (SIP).
2. Description of the Background Art
Integrated circuits (ICs) typically include metal conductive layers that are used to interconnect various individual devices of the IC. As the density of integrated circuits increases, more and more levels of metallization are employed to provide electrical connection between these devices.
The metal conductive layers are typically isolated from each other by one or more dielectric material layers. Holes (vias) formed through the dielectric layers provide electrical access between successive conductive interconnection layers.
For the current subhalf-micron (0.5 xcexcm) generation of semiconductor devices, any microscopic reaction at an interface between interconnection layers can cause degradation of the resulting integrated circuits (e.g., increase the resistivity of the interconnection layers). Barrier layers prevent degradation of interfaces between conductive and dielectric layers and have consequently become a critical component for improving the reliability of interconnect metallization schemes.
Refractory metals and their compounds, such as, for example, tantalum (Ta) and tantalum nitride (TaN) have been suggested as diffusion barriers for copper and other metallizations. Tantalum and tantalum-containing materials have low resistivity (resistivity less than about 15 xcexa9-cm), and show excellent performance in preventing the diffusion of copper into underlying layers as well in preventing the diffusion of fluorine and/or oxygen from low-k dielectric materials into the copper. In particular, tantalum-based barrier layers comprising two separate layers, a layer of tantalum deposited on a tantalum nitride layer, have been found particularly advantageous. The combination of these two layers provides excellent adhesion for copper as well as good barrier properties.
Physical vapor deposition (PVD) processes typically use a DC magnetron sputtering reactor. Such a sputter reactor includes a target composed of the layer to be sputter deposited along with a magnetron powered by a DC electrical source. The magnetron is scanned across the target thereby sputtering target material onto a substrate disposed inside the reactor.
However, conventional DC magnetron sputtering processes sputter atoms across a wide angular distribution that typically has a cosine dependence about the target. Such a wide distribution is disadvantageous for filling a high aspect ratio structure. This is because the off-angle sputtered particles preferentially deposits the barrier material around the upper corners of the high aspect ratio structure forming overhangs. Large overhangs on the high aspect ratio structures restrict the deposition of barrier material therein and at a minimum cause inadequate coverage along the sidewalls and bottom surfaces thereof.
One approach to ameliorate the overhang problem uses long-throw sputtering in a conventional reactor. In long-throw sputtering, the target is spaced relatively far from the substrate to be sputter coated. For example, the target-to-wafer spacing in long throw sputtering is typically greater than at least 50% of the wafer diameter. As such, the off-angle portion of the sputtering distribution is preferentially directed toward the chamber walls, while the central-angle portion remains directed toward the wafer. This truncated angular distribution for the sputtered material causes a higher fraction of the sputter particles to be directed into the high aspect ratio structure, thereby reducing the extent of overhangs thereon. However, the step-coverage of barrier layers formed using this sputter deposition technique may be discontinuous, particularly for high aspect ratio features.
Another PVD technique for depositing barrier layers in high aspect ratio features uses a high-density plasma (HDP) sputtering process. A high-density plasma sputtering process refers to a sputtering process having an average plasma density across the plasma of at least 1011 cmxe2x88x923. In HDP sputtering processes, a separate plasma source region is formed away from the substrate, for example, by inductively coupling RF power into an electrical coil wrapped around a plasma source region between the target and the substrate. The higher power ionizes not only the argon working gas, but also significantly increases the ionization fraction of the sputtered atoms. The substrate either self-charges to a negative potential or is RF biased to control its DC potential. The sputtered atoms are accelerated across the plasma sheath as they approach the negatively biased substrate. As a result, their angular distribution becomes strongly peaked in the forward direction so that they are drawn deeply into the high aspect ratio feature. Overhangs become much less of a problem in HDP sputtering, and bottom surface coverage as well as bottom sidewall coverage are relatively uniform in the center of the substrate.
However, HDP-deposited barrier layers typically have poor step coverage high up the sidewalls of high aspect ratio features. This is particularly true for high aspect structures located at the edges of the substrate. Furthermore, the sidewall coverage is typically asymmetric, with the side facing the center of the target being more heavily coated than the more shielded side facing a larger solid angle outside the target. This poor step coverage often results in voids and defects in the barrier layer, which then result in device failure.
Additionally, for some HDP sputtering processes a pressure of at least 30 milliTorr may be required. Such higher pressures for the high-density plasma produces a large number of inert gas ions, which may be accelerated across the plasma sheath toward the surface being sputter deposited. The high-energy inert gas ions may cause a number of problems such as the inadvertent embedding of inert gas ions in the deposited layer causing the surface morphology thereof to be rough, or even discontinuous, which then may result in device failure.
Therefore, a need exists for a method and apparatus for depositing a tantalum-containing barrier layer in high aspect ratio features.
A method of forming a tantalum-containing layer on a substrate is described. The tantalum-containing layer is formed using a physical vapor deposition technique wherein a magnetic field in conjunction with an electric field function to confine material sputtered from a tantalum-containing target within a reaction zone of a deposition chamber. The electric field is generated by applying a power of at least 8 kilowatts to the tantalum-containing target. The magnetic field is generated from a magnetron including a first magnetic pole of a first magnetic polarity surrounded by a second magnetic pole of a second magnetic polarity opposite the first magnetic polarity. The first magnetic pole preferably has a magnetic flux at least about 30% greater than a magnetic flux of the second magnetic pole. The deposition chamber may optionally comprise one or more shields positioned along sidewalls of the deposition chamber and adjacent to both the tantalum-containing target and the substrate. At least one of the one or more shields includes perforations through which reactive gases are provided to the deposition chamber.
The tantalum-containing layer deposition method is compatible with integrated circuit fabrication processes. In one integrated circuit fabrication process, an interconnect structure is formed. For such an embodiment, a preferred process sequence includes providing a substrate having a dielectric material thereon, wherein the dielectric material has one or more vias therein. One or more tantalum-containing barrier layers are deposited in the vias using a physical vapor deposition technique wherein a magnetic field in conjunction with an electric field function to confine material sputtered from a tantalum-containing target within a reaction zone of a deposition chamber. After the one or more tantalum-containing barrier layers are deposited in the vias, the interconnect structure is completed by filling the vias with a conductive material.